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| 1CY 621 48 fax id: 1079 PRELIMINARY CY62148 512K x 8 Static RAM Features * 4.5V-5.5V operation * CMOS for optimum speed/power * Low active power -- 660 mW (max.) * Low standby power (L version) -- 2.75 mW (max.) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE options an automatic power-down feature that reduces power consumption by more than 99% when deselected. Writing to the device is accomplished by taking chip enable one (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip enable one (CE) and output enable (OE) LOW while forcing write enable (WE). Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY62148 is available in a standard 450-mil-wide body width SOIC package. Functional Description The CY62148 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. This device has Logic Block Diagram Pin Configuration Top View SOIC A17 A16 A14 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 ROW DECODER I/O2 SENSE AMPS 512K x 8 ARRAY I/O3 I/O4 I/O5 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND CE WE COLUMN DECODER POWER DOWN I/O6 I/O7 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 OE 62148-1 Selection Guide CY62148-55 Maximum Access Time (ns) Maximum Operating Current Maximum CMOS Standby Current Shaded areas contain advance information CY62148-70 70 120 mA 2 mA 0.5 mA 55 Commercial Commercial L 120 mA 2 mA 0.5 mA Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 December 1996 - Revised July 31, 1997 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .....................................-0.5V to VCC +0.5V Range Commercial Industrial CY62148 DC Input Voltage[1] ................................. -0.5V to VCC +0.5V Current into Outputs (LOW) ........................................ 20 mA Operating Range Ambient Temperature[2] 0C to +70C -40C to +85C VCC 5V 10% 5V 10% Electrical Characteristics Over the Operating Range[3] 62148-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current -- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs GND VI VCC GND VI VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE VIH VIN VIH or VIN VIL, f = fMAX Max. VCC, CE VCC - 0.3V, VIN VCC - 0.3V, or VIN 0.3V, f=0 Com'l Test Conditions VCC = Min., IOH = -1 mA VCC = Min., IOL = 2.1 mA 2.2 -0.3 -1 -5 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 120 2.2 -0.3 -1 -5 Max. 62148-70 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 120 Max. Unit V V V V A A mA ISB1 Com'l 15 15 mA ISB2 Com'l L 2 500 2 500 mA A Shaded areas contain advance information Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters. 2 PRELIMINARY AC Test Loads and Waveforms R1 480 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255 5 pF INCLUDING JIG AND SCOPE (b) R2 255 GND 3ns 3.0V 90% 10% CY62148 5V OUTPUT R1 481 ALL INPUT PULSES 90% 10% 3 ns 109-3 109-4 Equivalent to: THEVENIN EQUIVALENT 167 1.73V OUTPUT Switching Characteristics[3,6] Over the Operating Range 62148-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE LOW to Low CE HIGH to High Z[7, 8] 3 20 0 55 55 45 45 0 0 45 45 0 3 20 70 60 60 0 0 50 55 0 3 25 0 70 Z[7, 8] Z[8] 0 20 3 25 3 55 20 0 25 55 55 3 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 62148-70 Min. Max. Unit CE LOW to Power-Up CE HIGH to Power-Down [9] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[8] WE LOW to High Z[7,8] Shaded areas contain advance information. Notes 6. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100pF load capacitance. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 3 PRELIMINARY Switching Waveforms Read Cycle No.1[10,11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID CY62148 62148-5 Read Cycle No. 2 (OE Controlled)[11,12] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB 62148-6 HIGH IMPEDANCE DATA OUT ICC Write Cycle No. 1 (CE Controlled)[13,14] tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA 62148-7 Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 4 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13,14] tWC ADDRESS tSCE CE CY62148 tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 15 tHZOE DATAIN VALID 62148-8 tHD Write Cycle No.3 (WE Controlled, OE LOW)[13,14] tWC ADDRESS tSCE CE tAW tSA WE tSD DATAI/O NOTE 15 tHZWE Note: 15. During this period the I/Os are in the output state and input signals should not be applied tHA tPWE tHD DATA VALID tLZWE 62148-9 5 PRELIMINARY Truth Table CE1 H X L L L OE X X L X H WE X X H L H I/O0 - I/O7 High Z High Z Data Out Data In High Z Mode Power-Down Power-Down Read Write Selected, Outputs Disabled Power Standby (I SB) Standby (I SB) Active (ICC) Active (ICC) Active (ICC) CY62148 Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current Conditions No input may exceed VCC + 0.5V VCC = VDR = 2.0V, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V Min. 2.0 (Com'l) (Ind'l) (Mil) tCDR tR Chip Deselect to Data Retention Time Operation Recovery Time 0 tRC 200 500 2 Max Unit V A A mA ns ns Ordering Information Speed (ns) 55 55 70 70 70 70 Ordering Code CY62148-55SC CY62148L-55SC CY62148-70SC CY62148L-70SC CY62148-70SI CY62148L-70SI Package Name S34 S34 S34 S34 S34 S34 Package Type 32-Lead (450-Mil) Molded SOIC 32-Lead (450-Mil) Molded SOIC 32-Lead (450-Mil) Molded SOIC 32-Lead (450-Mil) Molded SOIC 32-Lead (450-Mil) Molded SOIC 32-Lead (450-Mil) Molded SOIC Operating Range Commercial Commercial Commercial Commercial Industrial Industrial Shaded areas contain advance information. Document #: 38-00564-A 6 PRELIMINARY Package Diagrams 32-Lead (450 Mil) Molded SOIC S34 CY62148 7 |
Price & Availability of CY62148-55
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